# RISC-V native target configuration
# Bare-metal RISC-V execution โ no proof generation
[target]
name = "riscv"
display_name = "RISCV"
architecture = "register"
output_extension = ".elf"
[field]
prime = "2^64 - 2^32 + 1"
bits = 64
limbs = 1
[stack]
depth = 32
spill_ram_base = 0
[hash]
function = "Software"
digest_width = 0
rate = 0
[extension_field]
degree = 0
[cost]
tables = ["wall-clock"]
[status]
level = 3
lowering = "RegisterLowering"
lowering_path = "lir"
cost_model = false
tests = false
notes = "Native target. todo!() stubs in lowering."
trident/vm/riscv/target.toml
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